Home >  Term: FR0/FR1
FR0/FR1

FIFO receive-interrupt bits. Bits within the synchronous serial port control register (SSPCR) which set an interrupt trigger condition based on the number of words in the receive FIFO buffer.

0 0

Creator

  • Dedrick
  •  (Gold) 1101 points
  • 100% positive feedback
© 2025 CSOFT International, Ltd.