A field that indicates if a load TREG0 (LT/A/D/P/S) instruction loads only temporary register 0 (TREG0) or loads all three of the temporary registers (TREG0, TREG1, and TREG2) to maintain compatibility with the TMS320C2x. The TRM bit allows the TMS320C5x to operate in either ’C2x-compatible mode (TRM = 0) or ’C5x-enhanced mode (TRM = 1) in conjunction with the use of TREG0, TREG1, and TREG2. The TRM bit affects the operation of all ’C2x-compatible instructions that modify TREG0. This bit is stored in the processor mode status register (PMST).