The second stage of the master processor’s fetch, execute, access (FEA) pipeline and the third stage of the parallel processor’s fetch, address, execute (FAE) pipeline. These stages operate differently for the master processor and the parallel processors. For the master processor’s execute stage, the instruction is decoded, source operands are read from the registers, the operation is performed, and the results are written into the destination register. For the parallel processor, all data unit operations occur, as well as memory accesses (loads and stores) and register-to-register moves.