A 1-bit flag that transitions from 0 to 1 to indicate the data receive shift register (RSR) contents have been copied to the data receive register (DRR) and that data can be read. A receive interrupt (RINT) is generated upon the transition. The RRDY bit can be polled in software instead of using serial port interrupts. This bit is stored in the serial port control register (SPC) and TDM serial port control register (TSPC).